SC1005 DIGITAL LOGIC (3.0 AU)

Took this module in 21/22 Sem 1.

Components (Forgot exact percentages): LAMS, Lab assignments, Lab quiz, Midterm, Final

First half: Taught by Prof Chan Syin. Pre-recorded lectures must be watched before attending live lectures as it merely a recap + QnA session mostly. Content taught are: Number representation (binary, hex, oct, etc), boolean algebra, digital arithmetic, K-maps, logic circuits, digital circuits, Schmidt-Trigger, logic arrays. Explanations are good and easy to understand.

Second half: Taught by Prof Douglas Maskell. Pre-recorded lectures must be watched. Live lectures consists of recaps and live solves of past year final questions. Content taught are: Verilog programming, combinational circuits, sequential circuits, finite state machines. Pre-recorded lectures are clear and easy to understand. Watching live solves of PYP questions can be useful to understand the workflow and thought processes.

Labs: 5 compulsory labs. Each lab consists of a lab assignment, and then a 10 minute quiz at the end of the session. The assignments are simple and easy to follow. First half labs consists of circuitry using logic gates to light up LEDs. Second half was more abstract-using Verilog to print words on a FPGA board. Each assignment has to be checked by the lab instructor to receive full credit. The lab quiz was simple, but difficulty lies in the time crunch as 10 minutes can be short, since some questions require computations. The final lab quiz had 8 questions to be answered in 10 minutes! No surprise the lab quiz total median dropped by 3 points after the final quiz.

Midterm: Online quiz to be done in 50minutes. Good time management is needed, as the back questions carry higher weightage and no backtracking is allowed. If you do the first few questions slowly, you will definitely not have time for the back ones. My advice is to not waste too much time on a question and skip it instead. Spend more time on the back few questions.

Final: 1-hour paper consisting of MCQs and 4 long questions. The exam format changes regularly so do take note. The MCQs were straightfoward and mostly rehashed from 19/20 Sem 1 paper. I did that paper before the final and was shocked when most of the MCQs reappeared verbatim. Can’t complain about free marks. 😛 The long answer questions are mostly answered in Verilog. Make sure your Verilog syntax is solid, and avoid pitfalls like reg.

Overall: Content is pretty interesting, and some of the knowledge is needed for Computer Architecture and Organisation (1006). Make sure your first half knowledge is solid as most of the knowledge is carried over into the second half.